Some conventional high-withstand-voltage semiconductor elements are provided on a dielectric isolation substrate. The dielectric isolation substrate has an SOI (Silicon On Insulator) structure in which a silicon layer where elements are formed is provided on a support substrate with an insulating film in between.
Such a high-withstand-voltage semiconductor element needs a thick silicon layer having a thickness ranging from several μm to 10 μm depending on the target withstand voltage. Thus, the dielectric isolation substrate is fabricated by laminating two silicon wafers with a silicon oxide film in between and then grinding one of the silicon wafers until the thickness of the one silicon wafer reaches several μm to 10 μm.
However, when the silicon layer is thick, there is a problem that it takes a long time to diffuse impurities in the formation of a deep impurity diffusion layer extending from the front surface of the silicon layer to the silicon oxide film. Further, since the impurities are diffused also laterally, it may be difficult to obtain a desired impurity diffusion layer.
There is also a problem that it takes a long time to form an element isolation trench in the formation of a deep element isolation layer extending from the front surface of the silicon layer to the silicon oxide film. Further, it may be difficult to obtain a desired element isolation layer due to variations in etching rate.
As a result, there occurs a problem of deteriorating the element characteristics and element isolation characteristics of the high-withstand-voltage semiconductor element. Such deteriorations lower the fabrication yield and increase the fabrication cost, making stable fabrication of the high-withstand-voltage semiconductor element difficult.